Programmable frame splitter

ABSTRACT

A programmable frame splitter includes a plurality of programmable routers connected to a communication line. The routers contain logic to specify which bits of a frame of serial data are passed to an output of each of the routers. A control unit is provided having logic to control loading and startup of the routers. A field processing unit is provided to receive a bit-clock-out signal from each of the routers and serial data from the communication line. The field processing unit splits the frame of serial data into component fields and performs processing on the field.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention generally relates to digital telephony.More particularly, the present invention relates to splitting frames ofa serial data stream into component fields using a programmable framesplitter.

[0003] 2. Discussion of the Related Art

[0004] Digital telephony data is transmitted, serially, between a PBX(Private Branch Exchange) and a digital phone set. A PBX is a multi-lineswitching network that is typically located on the premises of abusiness. The switching network establishes connections between twoPBX-supported telephones or between a PBX-supported telephone and anoff-premises telephone. PBX/digital phone set transmission schemes aretypically proprietary.

[0005] A common transmission scheme uses short frames of information ona periodic basis. Within each frame there is a predetermined order offields. One of the key elements of implementing a telephony protocolstack is the ability to split the frame into component fields. While theproblem is easily solved by software using masking and shift operations,the data transmission rate and number of connections that eachmicroprocessor must support makes the solution computationallyintensive. As a further complication, telephony equipment is very costsensitive. Therefore, a microprocessor with the necessary processingpower is prohibitively expensive

[0006] The network most commonly used to support digital phones is theIntegrated Services Digital Network (ISDN). With ISDN, voice and dataare carried by bearer channels (B channels) occupying a bandwidth of 64Kbps (Kilobits per second). A data channel (D channel) handles signalingat 16 Kbps or 64 Kbps, depending on the service type. ISDN includes atleast two B-channels carrying user data and a D-channel that primarilycarries signaling data. The Basic Rate Interface (BRI) has twoB-channels and a single D-channel, possesses a bandwidth of 144 Kbps,and is sometimes referred to as a 2B+D interface to the ISDN.

[0007] The signaling capabilities of an ISDN are significantly superiorto the current public network supporting analog phones. Typically, keyphone systems and other private exchanges are connected to a publicswitched telephone network (PSTN) to provide voice communicationservice. In contrast to the conventional telephone network, an ISDNoffers a variety of features including multimedia communication servicesuch as voice, high-speed data and image communication services, andother additional non-voice communication services via network interfaceson the basis of digitization of the telephone network.

[0008] A PBX transmits to a digital phone set using proprietaryprotocols that typically follow many of the same principles as the ISDNprotocol. Therefore, a discussion of the ISDN data transmission schemeserves as a basis for understanding proprietary PBX/digital phoneprotocols.

[0009] In a U.S., the telephone company provides its BRI customers witha U-interface. The U-interface is a two-wire (single pair) interfacefrom the phone switch. It supports full-duplex data transfer over asingle pair of wires, therefore only a single device can be connected toa U-interface. This device is called a Network Termination 1 (NT−1). TheNT−1 functions as a frame splitter.

[0010] The NT−1 is a relatively simple device that converts the 2-wireU-interface into the 4-wire S/T interface. The S/T interface supportsmultiple devices (up to 7 devices may be placed on the S/T bus) because,while it is still a full-duplex interface, there is now a pair of wiresfor receive data, and another pair for transmit data.

[0011] Digital telephony data is transmitted to the U-interface. EachU-interface frame is 240 bits long. At the prescribed data rate of 160kbps, each frame is therefore 1.5 msec long. There are 216 2B+D bitsplaced in each 1.5-ms basic frame.

[0012] The B₁- and B₂-channels and the D-channel (subrate channels) aremultiplexed in a basic frame. A channel occupies an integer number oftime slots and is in the same time-slot position in every frame. The B₁-and B₂-channels and the D-channel may be thought of as component fields.To demultiplex the B₁- and B₂-channels and the D-channel, it isnecessary to split the basic frame into the component fields. For ISDN,this is accomplished by the NT−1 frame splitter.

[0013] Frame splitting typically relies on a dedicated hardwareimplementation to split the frames of the serial data stream intofields. One such implementation is shown in FIG. 1. The inputs into thesplitter are: 1) a frame start signal, and 2) a bit clock. The outputfor each field is an envelope signal that specifies the time of thefield. Components that process the field data use 1) a serial datastream, 2) the bit clock, and 3) the field envelope to extract thefield's data.

[0014] When using a fixed frame splitter, a new hardware design isneeded as each protocol stack is implemented. This arrangement resultsin a proliferation of designs that must be debugged, documented, andmaintained. Therefore, there is a need for a programmable frame splitterthat does not require a dedicated hardware implementation to split theserial data into component fields.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015]FIG. 1 illustrates a dedicated hardware implementation to splitserial data into component fields according to the prior art;

[0016]FIG. 2 illustrates a programmable frame splitting system to splitserial data into component fields according to an embodiment of thepresent invention;

[0017]FIG. 3 illustrates a timing diagram of a sample router outputaccording to an embodiment of the present invention;

[0018]FIG. 4 illustrates a schematic diagram of a single routeraccording to an embodiment of the present invention;

[0019]FIG. 5 illustrates a flow chart for implementation of the routertable;

[0020]FIG. 6 illustrates a flow chart for implementation of theprogrammable frame splitting system; and

[0021]FIG. 7 illustrates memory devices of a single router according toan alternative embodiment of the invention.

DETAILED DESCRIPTION

[0022]FIG. 2 illustrates a programmable frame splitting system 200according to an embodiment of the present invention. The programmableframe splitting system includes a communication line 201, a programmableframe splitter 280 containing a set of programmable routers 220, 230,240 with logic that controls the loading and startup of the routers, andfield processing units 250, 260, 270.

[0023] Each router 220, 230, 240 operates independently and containsRandom Access Memory (RAM) that is programmable on a bit-by-bit basis topass through any combination of frame bits. RAM is considered “randomaccess” because any memory cell may be accessed directly based on anaddress.

[0024] RAM devices fall into two general categories: static or dynamic.Static RAMs hold their contents for as long as power is applied. DynamicRAMs “forget” their contents after a short period (a few seconds) unlessthey are refreshed. The refresh circuitry is fairly easy to implement,however, while the memory is being refreshed it can not be accessed.Therefore, static memories are normally used in timing criticalapplications when the contents of the memory must be available at alltimes.

[0025] Static memories are further divided into two main types:asynchronous or synchronous. For asynchronous memories, an address ispresented at the input to the memory and a short time later the dataappears at the outputs. Synchronous memories require an additional clockinput. All functions of the memory (read and write) occur in relation tothe clock. Typically, the rising edge of the clock is used to sample theaddress lines and the next rising edge presents the data at the outputs.

[0026] In addition, static memories can be either single-ported ordual-ported. In a single-port memory there is one input address bus,reading or writing to the memory is controlled by a Read/Write input.Dual-ported memories have a read address bus and a write address bus.One bus is used to read the memory, and the other to write the memory.As an added feature you can read and write the memory simultaneously.

[0027] Any of the above types of RAM memory may be used to implement therouter. FIG. 4, shows one embodiment using a dual-ported synchronousstatic RAM. Alternatively, a dual-ported asynchronous static RAM may beused by removing the system clock input 402. A single-ported memory canbe used by addition of a control to multiplex the microprocessor's busand the address counter. By being creative with the refresh cycles adynamic RAM may be used. In yet another embodiment of the presentinvention, the RAM may be part of a Field Programmable Gate Array(FPGA).

[0028] A field processing unit 250, 260, 270 is a hardware componentthat extracts a single field and performs some form of processing. Forexample, a voice field-processing unit converts the digital voice datainto an analog signal suitable for a headset. When implementing theprogrammable frame splitter, one router is allocated for each fieldprocessing unit. There are as many field processing units as theparticular application requires. The programmable splitter 280 does notknow (or care) what the field processing unit does. The programmablesplitter 280 blindly passes the field data to the field processing unit.

[0029] The programmable splitter 280 does not create frame envelopes,but instead uses a scheme of “gating” the bit clock 204. For example,this gating is achieved by combining the output of the RAM router tableDout 406 (see FIG. 4) with the bit-clock-in signal 204 via an AND gate430.

[0030] The timing diagram of FIG. 3 illustrates a hypothetical framethat contains six data bits 302 of the bit-clock-in signal 204. Thisframe of data is “gated”, i.e., combined with the router table outputDout 406 pattern 010110 via the AND gate 430 to produce thebit-clock-out signal 408. The RAM router table contains a row of datawith the pattern 010110 that is addressed by the address counter 410 andpassed to Dout 406. A hypothetical output of a router is shown by thelast line 408 of FIG. 3. This router has been programmed to pass bits2,4,5 of the frame.

[0031]FIG. 4 shows a schematic of a single router 400. Each router 400contains a table that specifies which bits of a frame should be passedto the router's output 408. The table may be implemented with a N×1 RAMmemory 420 and a address counter 410, where N, for example, is thenumber of bits equal to the largest possible frame size. N may be largerthan a given frame size, but may not be smaller. N may be larger becausethe address counters are reset at the start of each frame. Whenimplementing a splitter, N would be selected to correspond to thelargest possible frame size. This implementation allows processing anyframe N (or less) bits long. In one embodiment of the present invention,the RAM 420 and address counter 410 are part of a Field ProgrammableGate Array (FPGA).

[0032] The N×1 RAM contains one column of data N bits long. The addresscounter contains N addresses that are addressed sequentially using thebit-clock-in 204 and frame start signal 203. Each bit of data in the RAMrouter table is addressed separately by the address counter 410. Theframe start signal 203 is used as a synchronizing signal to tell therouter 400 when to restart at the beginning of the RAM data table. Thisapproach is accomplished by using the frame start signal 203 to resetthe address counter 410. The frame start signal 203 is typicallygenerated externally.

[0033] A system clock 402 is input into the N×1 RAM and the D flip-flop440 to provide synchronization of the system.

[0034]FIG. 5 illustrates a flow chart for implementation of the routertable. At the start 510 of each frame the frame start bit 301 causes theaddress counter 410 to reset to zero 520. Then, the address counter 410increments a new address at each bit time 530. As the address counter410 increments, an address is provided to the RAM and the next tablevalue is read and passed to Dout 406. When a table value of one ispassed as Dout 406 to the AND gate 430, it causes the bit-clock-insignal 204 to be passed 540 as the bit-clock-out signal 408. When atable value of zero is passed as Dout 406 to the AND gate 430 it causesbit-clock-out signal 408 to be zero 550.

[0035] In addition to the set of routers 220, 230, 240, the programmablesplitter 280 of FIG. 2 includes a control unit 210 that contains controllogic that facilitates the writing of data into the various routertables 220, 230, 240, and ensures the orderly startup of each router,220, 230, 240.

[0036] The control unit 210 provides access from the microprocessor tothe router memory. Its implementation depends on the router'simplementation. If the router 400 uses dual-ported memory theimplementation is very simple; some address decoders and a flip-flopthat the microprocessor sets to start the routers. If the router usessingle-ported memory the implementation is more complex as the unit mustcontrol the multiplexing of the microprocessor bus and the addresscounter. For dynamic memory the control unit will have to contain therefresh circuitry.

[0037] The microprocessor bus 202 provides a data path for transmissionof data bits from a microprocessor to the software configurable routertables. The data written into the router table selects, on a bit-by-bitbasis, which bits of the bit-clock-in signal are passed through the ANDgate 430 as the bit-clock-out signal 408. Referring to FIG. 3, to createthe required bit-clock-out, the pattern 010110 is written into therouter table. Generating the data to write into the router table is thetask of the system engineer who uses the splitter component. Thesplitter component is only a small part of an overall system to processframe data. The system engineer must know the layout of the frame (i.e.,the fields), which fields need to be processed and how the fields needto be processed. Once it is determined, the engineer designs (or reuseexisting) field-processing units 250, 260, 270. The number of fieldprocessing units 250, 260, 270, in turn, determines the number ofrouters 220, 230, 240, in the splitter. The data written to each routertable is generated so that only the field required by the respectivefield-processing unit 250, 260, 270, is passed through the router 220,230, 240.

[0038] Once the router tables are initialized and the splitter isstarted, the splitter runs continuously without need for softwareintervention.

[0039]FIG. 6 illustrates a flow chart for the implementation of theprogrammable frame splitting system 200. A control unit 210 receives 610data to program the routers 220, 230, 240, from a bus 202 (e.g. linescoupled to a microprocessor) and writes the data to the appropriatesoftware configured router table. The router table is now programmed toextract a particular field from a frame of serial data. The control unit210 initiates the startup of the appropriate routers 220, 230, 240 inanticipation of the receipt of a serial data stream on the communicationline 201. Arrival of serial data stream initiates generation of framestart signal 620. For a particular router, at the start of each frame203 the address counter 410 is reset 630 to zero and then increments ateach bit time. As the address counter 410 increments 640, an address isprovided to the RAM 420 and the next table value is read and passed toDout 406. The output 406 of the RAM router table Dout is combined withthe bit-clock-in signal 204 via the AND gate 430 to produce a gating 650of the bit-clock-in signal. The output of the AND gate 407 is passed tothe D flip-flop 440 to provide synchronization 660 with the system clock402. The bit-clock-out signal is passed to the appropriate fieldprocessing unit 250, 260, 270 to extract 670 the field from the serialdata stream 201 and provide further processing of the field.

[0040]FIG. 7 illustrates an alternative embodiment of the invention. Asingle router 220, 230, 240, contains a router table. The router tablemay be implemented by a N bit register 701 and a N bit shift register702. A control unit 210 receives 610 data to program the routers 220,230, 240, from a bus 202 (e.g. lines coupled to a microprocessor) andwrites the data to the appropriate software configured router table. Inthe alternative embodiment the bus data 202 is written into the N bitregister 701. The frame start signal 203 causes the data to be parallelshifted into the N bit shift register 702. The bit-clock-in signal 204causes the data to be serially shifted out, one bit at a time. Theoutput of the N bit shift register Dout 406 is combined with thebit-clock-in signal 204 via the AND gate 430 to produce a gating 650 ofthe bit-clock-in signal 204. The output of the AND gate 407 is passed tothe D flip-flop 440 to provide synchronization 660 with the system clock402. The bit-clock-out signal is passed to the appropriate fieldprocessing unit 250, 260, 270 to extract 670 the field from the serialdata stream 201 and provide further processing of the field.

[0041] In summary, the invention is a programmable frame splitter thatis flexible enough to handle any frame configuration, includingnon-continuous fields. By allowing the software to reconfigure thefields, the invention allows for rapid implementation of new protocolsand reduces overall hardware costs by introducing a commonality ofcomponents.

[0042] In prior designs, framing splitting used hardcoded counters andmultiplexers requiring new implementations for each protocol. Theproposed invention removes the hardcoding and replaces it with softwareconfigurable tables. This configuration allows the support of newprotocols without the need to design new hardware. A programmable framesplitter, according to the invention, requires only that new tables bedevised.

[0043] While the description above refers to particular embodiments ofthe present invention, it will be understood that many modifications maybe made without departing from the spirit thereof The accompanyingclaims are intended to cover such modifications as would fall within thetrue scope and spirit of the present invention. The presently disclosedembodiments are therefore to be considered in all respects asillustrative and not restrictive, the scope of the invention beingindicated by the appended claims, rather than the foregoing description,and all changes that come within the meaning and range of equivalency ofthe claims are therefore intended to be embraced therein.

What is claimed is:
 1. A programmable frame splitter, comprising: aplurality of programmable routers connected to a communication line,each of said routers having logic to control loading and startup of saidrouters, and logic to specify which bits of a frame of serial data ispassed to an output of each of said routers; and a plurality of fieldprocessing units to receive a bit clock out signal from each of saidrouters and serial data from the communication line, wherein each ofsaid field processing units splits the frame of serial data intocomponent fields and performs processing on the component fields.
 2. Theprogrammable frame splitter according to claim 1, wherein the logiccontrolling the loading and startup of said routers is contained in acontrol unit.
 3. The programmable frame splitter according to claim 1,wherein the control unit receives a bus signal, a frame start signal,and a bit-clock-in signal.
 4. The programmable frame splitter accordingto claim 1, wherein the component fields include voice, video, and data.5. The programmable frame splitter according to claim 1, wherein thelogic to specify which bits of the frame of serial data is passed to theoutput of each of said routers is implemented utilizing at least onememory device.
 6. The programmable frame splitter according to claim 5,wherein the logic is implemented with a N×1 memory device and an addresscounter, where N is a number of bits equal to the largest possible framesize.
 7. The programmable frame splitter according to claim 5, whereinthe logic is implemented with a N bit register and a N bit shiftregister, where N is a number of bits equal to the largest possibleframe size.
 8. A programmable frame splitter, comprising: a plurality ofprogrammable routers connected to a communication line, each of saidrouters containing logic to specify which bits of a frame of serial datais passed to an output of each of said routers; a control unit havinglogic to control loading and startup of said routers; and a plurality offield processing units to receive a bit-clock-out signal from each ofsaid routers and serial data from the communication line, each of saidfield processing units splitting the frame of serial data into componentfields and performing processing on the component fields.
 9. Theprogrammable frame splitter according to claim 8, wherein the controlunit receives a bus signal, a frame start signal, and a bit-clock-insignal.
 10. The programmable frame splitter according to claim 8,wherein the component fields include voice, video and data.
 11. Theprogrammable frame splitter according to claim 8, wherein the logic tospecify which bits of the frame of serial data is passed to the outputof each of said routers is implemented utilizing at least one memorydevice.
 12. The programmable frame splitter according to claim 11,wherein the logic is implemented with a N×1 memory device and an addresscounter, where N is a number of bits equal to the largest possible framesize.
 13. The programmable frame splitter according to claim 11, whereinthe logic is implemented with a N bit register and a N bit shiftregister, where N is a number of bits equal to the largest possibleframe size.
 14. A program code storage device, comprising: amachine-readable storage medium; and machine-readable program code,stored on the machine-readable storage medium, having instructions toreceive a bus signal, a frame start signal, and a bit-clock-in signal,write data received from a bus into a router table of a plurality ofprogrammable routers, initiate startup of the plurality of programmablerouters, determine which bits of a frame of serial data is passed to anoutput of each of the routers as a bit-clock-out signal; and process thebit-clock-out signal from each of said routers and serial data from acommunication line, wherein the frame of serial data is split intocomponent fields.
 15. The program code storage device according to claim14, wherein each of the programmable routers operates independently andis programmable on a bit-by-bit basis to pass any combination of framebits, and each one of the routers contains a table of data, receivedfrom a control unit via the bus, said data specifying which bits of theframe is passed to each of the routers' output as the bit-clock-outsignal.
 16. The machine-readable program code storage device accordingto claim 14, wherein the router table is implemented with a N×1 memorydevice and an address counter, where N is a number of bits equal to alargest possible frame size.
 17. The machine-readable program codestorage device according to claim 14, wherein the router table isimplemented with a N bit register and a N bit shift register, where N isa number of bits equal to a largest possible frame size.
 18. Themachine-readable program code storage device according to claim 14,wherein the router table is implemented utilizing at least one memorydevice.
 19. A programmable frame splitting system, comprising: acommunication line; a plurality of programmable routers connected tosaid communication line, wherein each of said routers contains logic tospecify which bits of a frame of serial data is passed to an output ofeach router; a control unit containing logic to control loading andstartup of said routers; and a plurality of field processing units toreceive a bit clock out signal from each of said routers and serial datafrom the communication line, wherein each of said field processing unitssplits the frame of serial data into component fields and performsprocessing on the component fields.
 20. The programmable frame splittingsystem according to claim 19, wherein the control unit receives a bussignal, a frame start signal, and a bit clock in signal.
 21. Theprogrammable frame splitting system according to claim 19, wherein thecomponent fields include voice, video and data.
 22. The programmableframe splitter system according to claim 19, wherein the logic tospecify which bits of the frame of serial data is passed to the outputof each of said routers is implemented utilizing at least one memorydevice.
 23. The programmable frame splitter according to claim 22,wherein the logic is implemented with a N×1 memory device and an addresscounter, where N is a number of bits equal to the largest possible framesize.
 24. The programmable frame splitter according to claim 22, whereinthe logic is implemented with a N bit register and a N bit shiftregister, where N is a number of bits equal to the largest possibleframe size.
 25. A method of programmable frame splitting, comprising:receiving a bus signal, a frame start signal, and a bit-clock-in signal;writing data received from a bus into a router table of a plurality ofprogrammable routers, initiating startup of the plurality ofprogrammable routers; determining which bits of a frame of serial datais passed to an output of each of the routers as a bit-clock-out signal;and processing the bit-clock-out signal from each of said routers andserial data from the communication line, wherein the frame of serialdata is split into component fields and each component field isprocessed.
 26. The method according to claim 25, wherein each of theprogrammed routers operates independently and is programmable on abit-by-bit basis to pass any combination of frame bits, wherein each oneof the routers contains a table of data, received from a control unitvia the bus, said data specifying which bits of the frame is passed toeach of the routers' output as the bit-clock-out signal.
 27. The methodaccording to claim 26, wherein the table is implemented with a N×1memory device and an address counter, where N is a number of bits equalto a largest possible frame size.
 28. The method according to claim 26,wherein the table is implemented with a N bit register and a N bit shiftregister, where N is a number of bits equal to a largest possible framesize.
 29. The method according to claim 26, wherein the table isimplemented utilizing at least one memory device.
 30. The methodaccording to claim 25, wherein the determining of which bits of theframe is passed to each of the routers' output as the bit-clock-outsignal, at start of each frame an address counter is reset to zero andthen increments at each bit time, as the address increments a next tablevalue is read, and a value of one causes the bit-clock-in signal to bepassed as the bit-clock-out signal, while a value of zero causes thebit-clocked-out signal to be negated.